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AMD Ryzen, Faster Memory, and the Infinity Fabric
AMD Ryzen AMD Ryzen AMD Ryzen AMD Ryzen AMD Ryzen AMD Ryzen AMD Ryzen AMD Ryzen 1 00:00:00,030 --> 00:00:04,470 following the initial release of AMD 2 00:00:02,760 --> 00:00:07,109 Rison there was a ton of discussion 3 00:00:04,470 --> 00:00:09,540 regards to using higher clocked system 4 00:00:07,109 --> 00:00:10,950 ram particularly in games the 5 00:00:09,540 --> 00:00:12,599 performance benefits of having higher 6 00:00:10,950 --> 00:00:14,400 clock memory was something that we 7 00:00:12,599 --> 00:00:16,350 didn't necessarily see an Intel side 8 00:00:14,400 --> 00:00:18,420 it's just not now the architecture is 9 00:00:16,350 --> 00:00:20,340 made it's not made to benefit from 10 00:00:18,420 --> 00:00:21,689 higher clock memory but rise ins 11 00:00:20,340 --> 00:00:23,400 architecture is and that's what I want 12 00:00:21,689 --> 00:00:26,580 to talk about in this video if it's 13 00:00:23,400 --> 00:00:28,980 worth buying really expensive high clock 14 00:00:26,580 --> 00:00:30,929 RAM out of the box for the sake of a 15 00:00:28,980 --> 00:00:33,120 rise in CPU and a lot of the people who 16 00:00:30,929 --> 00:00:34,860 spend you know 400 bucks on an 1800 X 17 00:00:33,120 --> 00:00:36,420 are probably gonna buy a higher clock to 18 00:00:34,860 --> 00:00:39,360 rise in memory anyway at least a memory 19 00:00:36,420 --> 00:00:40,500 that's capable of reaching 3000 or 3,200 20 00:00:39,360 --> 00:00:41,670 maker it's on the rise in platform which 21 00:00:40,500 --> 00:00:43,469 is difficult to do we'll talk about that 22 00:00:41,670 --> 00:00:46,079 as well but for those who are in the 23 00:00:43,469 --> 00:00:48,030 mid-range Rison five-tier should you 24 00:00:46,079 --> 00:00:50,219 still consider fast memory and why does 25 00:00:48,030 --> 00:00:57,629 it even matter in the first place I talk 26 00:00:50,219 --> 00:01:00,149 about all that in this video now when it 27 00:00:57,629 --> 00:01:02,640 comes down to it all rise in CPUs on a 28 00:01:00,149 --> 00:01:04,350 fabrication level are basically the same 29 00:01:02,640 --> 00:01:05,580 there are a few imperfections in some of 30 00:01:04,350 --> 00:01:07,229 the cores and that is ultimately 31 00:01:05,580 --> 00:01:09,780 differentiates a rise in three cpu from 32 00:01:07,229 --> 00:01:11,580 a rise in seven cpu so of the eight 33 00:01:09,780 --> 00:01:12,600 cores that are packed into every Rison 34 00:01:11,580 --> 00:01:15,540 chip no matter if you have a rise in 35 00:01:12,600 --> 00:01:17,310 three up to Horizon seven CPU if four of 36 00:01:15,540 --> 00:01:18,509 those aren't doing too well then AMD is 37 00:01:17,310 --> 00:01:19,830 gonna just disable and they're just 38 00:01:18,509 --> 00:01:21,840 gonna turn them off it's better than 39 00:01:19,830 --> 00:01:23,880 making an entirely new fabrication 40 00:01:21,840 --> 00:01:25,680 process for a four core chip this way 41 00:01:23,880 --> 00:01:27,299 they can save money makes perfect sense 42 00:01:25,680 --> 00:01:28,890 I don't blame them for doing that so a 43 00:01:27,299 --> 00:01:30,720 before remaining course if these can 44 00:01:28,890 --> 00:01:33,210 handle power loads pretty well and the 45 00:01:30,720 --> 00:01:35,400 the performance degradation isn't too 46 00:01:33,210 --> 00:01:39,090 substantial then these might be arisin 47 00:01:35,400 --> 00:01:40,619 five 1400s or 1500 X's if they aren't 48 00:01:39,090 --> 00:01:43,110 doing too well with handling a lot of 49 00:01:40,619 --> 00:01:44,850 power and the schedulers aren't doing 50 00:01:43,110 --> 00:01:46,409 that great a job at increasing the 51 00:01:44,850 --> 00:01:48,509 performance level then they might be 52 00:01:46,409 --> 00:01:50,130 rising three CPUs with multi-threading 53 00:01:48,509 --> 00:01:52,290 and disabled so it really comes down to 54 00:01:50,130 --> 00:01:55,200 what AMD deems as acceptable on both 55 00:01:52,290 --> 00:01:57,000 power delivery and execution levels now 56 00:01:55,200 --> 00:01:58,710 the difference between AMD and Intel 57 00:01:57,000 --> 00:02:01,799 because Intel does this too with bidding 58 00:01:58,710 --> 00:02:03,420 is that AMD decides well if these four 59 00:02:01,799 --> 00:02:06,180 cores aren't going to cut it we're gonna 60 00:02:03,420 --> 00:02:08,369 disable two of the cores in one cc X 61 00:02:06,180 --> 00:02:11,250 which is a four core cluster in a Rison 62 00:02:08,369 --> 00:02:13,280 CPU and two cores in the other CC X 63 00:02:11,250 --> 00:02:16,069 which is the other cluster of 64 00:02:13,280 --> 00:02:18,560 horizon CPU every rise in CPU has to CC 65 00:02:16,069 --> 00:02:20,209 x's per die the red Ripper has four 66 00:02:18,560 --> 00:02:22,670 which is why you can get up to 16 cores 67 00:02:20,209 --> 00:02:24,470 in those CPUs maybe this diary shot will 68 00:02:22,670 --> 00:02:26,180 help explain things a bit better so if 69 00:02:24,470 --> 00:02:27,740 two cores are activated in one cc X and 70 00:02:26,180 --> 00:02:29,630 two are activated in the other there has 71 00:02:27,740 --> 00:02:31,040 to be some sort of efficient way for 72 00:02:29,630 --> 00:02:32,930 them both to communicate because these 73 00:02:31,040 --> 00:02:35,000 are essentially two separate dies they 74 00:02:32,930 --> 00:02:36,890 might not be that physically but each 75 00:02:35,000 --> 00:02:39,620 core cluster has an own set of resources 76 00:02:36,890 --> 00:02:41,330 including l3 cache which means that when 77 00:02:39,620 --> 00:02:43,040 you're in especially intense situations 78 00:02:41,330 --> 00:02:44,480 on a computational level and they have 79 00:02:43,040 --> 00:02:47,330 to share information and process 80 00:02:44,480 --> 00:02:49,970 information simultaneously and exchange 81 00:02:47,330 --> 00:02:52,190 resources there has to be an efficient 82 00:02:49,970 --> 00:02:54,380 Highway a way for data to be transferred 83 00:02:52,190 --> 00:02:57,050 super quick between the cores to 84 00:02:54,380 --> 00:02:59,660 eliminate that latency this highway is 85 00:02:57,050 --> 00:03:01,489 called the Infinity fabric as Tom's 86 00:02:59,660 --> 00:03:02,750 Hardware puts it the large amount of 87 00:03:01,489 --> 00:03:05,060 data flowing through this pathway 88 00:03:02,750 --> 00:03:07,430 requires a lot of scheduling magic to 89 00:03:05,060 --> 00:03:09,080 ensure a high quality of service it's 90 00:03:07,430 --> 00:03:11,330 also logical to assume that these six 91 00:03:09,080 --> 00:03:14,090 and four core models benefit from less 92 00:03:11,330 --> 00:03:15,140 cross CCX traffic compared to the eight 93 00:03:14,090 --> 00:03:16,430 core models 94 00:03:15,140 --> 00:03:19,579 so they're actually hinting at here is 95 00:03:16,430 --> 00:03:22,040 the dual CCX design is a blessing in a 96 00:03:19,579 --> 00:03:23,630 way and a curse it's a blessing for AMD 97 00:03:22,040 --> 00:03:25,519 from a financial standpoint because all 98 00:03:23,630 --> 00:03:27,709 they have to do is slap multiple CC exes 99 00:03:25,519 --> 00:03:29,720 into the same chip and just run infinity 100 00:03:27,709 --> 00:03:31,100 fabric all between them which saves them 101 00:03:29,720 --> 00:03:32,600 money because they can control how many 102 00:03:31,100 --> 00:03:34,100 CC exes are in each dial without 103 00:03:32,600 --> 00:03:36,680 completely redoing the fabrication 104 00:03:34,100 --> 00:03:39,380 process but the curse involved is the 105 00:03:36,680 --> 00:03:41,870 latency involved between the CC X data 106 00:03:39,380 --> 00:03:44,239 transfers so the Infinity fabric itself 107 00:03:41,870 --> 00:03:46,820 is not the most efficient means by which 108 00:03:44,239 --> 00:03:49,250 data is transferred from one CC X to 109 00:03:46,820 --> 00:03:50,480 another this is where the faster memory 110 00:03:49,250 --> 00:03:52,549 comes into play it's but this whole 111 00:03:50,480 --> 00:03:54,170 video is about why rise and benefits 112 00:03:52,549 --> 00:03:55,310 from faster memory we hear people say 113 00:03:54,170 --> 00:03:57,859 that maybe they don't know what they're 114 00:03:55,310 --> 00:03:59,690 talking about but they are correct in a 115 00:03:57,859 --> 00:04:01,850 sense it really depends on the number of 116 00:03:59,690 --> 00:04:04,489 cores enabled per cc X but ultimately 117 00:04:01,850 --> 00:04:06,470 Rison will benefit more from faster 118 00:04:04,489 --> 00:04:07,940 memory than Intel will and the reason 119 00:04:06,470 --> 00:04:09,769 why is because the Infinity fabrics 120 00:04:07,940 --> 00:04:12,049 speed this the rate at which it can 121 00:04:09,769 --> 00:04:14,600 transfer data is directly tied to the 122 00:04:12,049 --> 00:04:16,640 frequency of your system memory Intel is 123 00:04:14,600 --> 00:04:19,400 independent on the same variable because 124 00:04:16,640 --> 00:04:22,580 their consumer-grade CPUs are reliant on 125 00:04:19,400 --> 00:04:24,960 the ring bus design two rings share 126 00:04:22,580 --> 00:04:26,820 information between let's say 4 cores 127 00:04:24,960 --> 00:04:29,789 and basically you have less traffic 128 00:04:26,820 --> 00:04:32,009 being dispatched between cores so the 129 00:04:29,789 --> 00:04:34,410 the congestion isn't as great as it 130 00:04:32,009 --> 00:04:36,120 would be on an 8-core Rison cpu because 131 00:04:34,410 --> 00:04:37,620 then you have four cores trying to share 132 00:04:36,120 --> 00:04:40,020 information down let's say a single 133 00:04:37,620 --> 00:04:41,130 pathway with the Infinity fabric so 134 00:04:40,020 --> 00:04:43,949 there can be quite a bit of congestion 135 00:04:41,130 --> 00:04:46,320 and lag I shouldn't say lag it's more or 136 00:04:43,949 --> 00:04:49,169 less a gamer term but latency it's the 137 00:04:46,320 --> 00:04:50,880 delay in data transfer and we see a huge 138 00:04:49,169 --> 00:04:53,190 difference between the rain bus design 139 00:04:50,880 --> 00:04:56,250 with Intel a comparable Intel CPU and 140 00:04:53,190 --> 00:04:59,550 the Infinity fabric whereas cores on an 141 00:04:56,250 --> 00:05:03,120 i7 7 700 K rely on the latency roughly 142 00:04:59,550 --> 00:05:06,330 between 30 and 40 nanoseconds cross 143 00:05:03,120 --> 00:05:09,570 quartic or latency on a cc x-ray for 144 00:05:06,330 --> 00:05:12,630 Horizon is somewhere in the realm of 200 145 00:05:09,570 --> 00:05:14,940 nanoseconds almost 10 times the latency 146 00:05:12,630 --> 00:05:17,039 just because data has to be transferred 147 00:05:14,940 --> 00:05:19,320 across an infinity fabric not to be 148 00:05:17,039 --> 00:05:21,419 frank we're talking nanoseconds here not 149 00:05:19,320 --> 00:05:22,650 even milliseconds but it does add up 150 00:05:21,419 --> 00:05:24,990 over time as huge computational 151 00:05:22,650 --> 00:05:26,940 workloads bottleneck that infinity 152 00:05:24,990 --> 00:05:29,010 fabric you can imagine how things get 153 00:05:26,940 --> 00:05:30,330 pretty backed up in the long run and you 154 00:05:29,010 --> 00:05:33,510 might even be able to tell a difference 155 00:05:30,330 --> 00:05:35,550 in things like games and also in render 156 00:05:33,510 --> 00:05:37,470 times if you do have heavy workloads 157 00:05:35,550 --> 00:05:39,419 being pushed to rise in CPUs they might 158 00:05:37,470 --> 00:05:42,270 not be able to handle them as well with 159 00:05:39,419 --> 00:05:44,789 that lower clocked system Ram so there 160 00:05:42,270 --> 00:05:46,470 you have it yes AMD rice and CPUs do 161 00:05:44,789 --> 00:05:47,880 benefit from higher clock memory it's 162 00:05:46,470 --> 00:05:50,340 not a myth and the reason why is because 163 00:05:47,880 --> 00:05:51,900 AMD employs infinity fabric which is 164 00:05:50,340 --> 00:05:53,940 directly dependent on the speed of your 165 00:05:51,900 --> 00:05:55,289 RAM now getting too much into detail 166 00:05:53,940 --> 00:05:57,060 that's really all you need to know 167 00:05:55,289 --> 00:05:58,620 something else worth noting is that rise 168 00:05:57,060 --> 00:06:00,360 in 3cp is because they only have two 169 00:05:58,620 --> 00:06:01,919 cores activated per CCX aren't going to 170 00:06:00,360 --> 00:06:04,740 benefit as much from the higher clocked 171 00:06:01,919 --> 00:06:07,020 Ram only because the data transfer rates 172 00:06:04,740 --> 00:06:09,870 between CC X's are going to be as high 173 00:06:07,020 --> 00:06:11,849 because only two cores per CC X are 174 00:06:09,870 --> 00:06:15,720 actually sending information whereas in 175 00:06:11,849 --> 00:06:17,550 horizon 7 1700 700 X or 800 X CPU get 176 00:06:15,720 --> 00:06:19,020 four cores on each side sending a ton of 177 00:06:17,550 --> 00:06:21,270 information things can get pretty 178 00:06:19,020 --> 00:06:22,289 congested in there for more info on this 179 00:06:21,270 --> 00:06:24,060 maybe you'd like to read an article 180 00:06:22,289 --> 00:06:25,169 about the Infinity fabric I invite you 181 00:06:24,060 --> 00:06:26,430 to check out the link at the top this 182 00:06:25,169 --> 00:06:27,900 video's description sometimes it helps 183 00:06:26,430 --> 00:06:29,639 to just read something over and over 184 00:06:27,900 --> 00:06:31,320 until it clicks each it takes me 5 or 6 185 00:06:29,639 --> 00:06:33,330 times I'm like I'm like you're bringing 186 00:06:31,320 --> 00:06:35,250 the sentence until till something clicks 187 00:06:33,330 --> 00:06:36,330 you get that light bulb go off now ok I 188 00:06:35,250 --> 00:06:37,199 get it now 189 00:06:36,330 --> 00:06:38,669 it's harder to do that with a 190 00:06:37,199 --> 00:06:39,930 videocassette to keep hearing me say it 191 00:06:38,669 --> 00:06:41,490 over and over again it's less annoying 192 00:06:39,930 --> 00:06:42,990 when you're doing it yourself in your 193 00:06:41,490 --> 00:06:44,069 head and invite you to check that link 194 00:06:42,990 --> 00:06:46,110 out by the way it's linked to Tom's 195 00:06:44,069 --> 00:06:47,669 hardware and they have a great article 196 00:06:46,110 --> 00:06:49,080 breaking down the Infinity fabric and 197 00:06:47,669 --> 00:06:50,460 why it behaves the way it does also is a 198 00:06:49,080 --> 00:06:52,800 pretty cool benchmarks in there to back 199 00:06:50,460 --> 00:06:53,610 up the claims made in this video if you 200 00:06:52,800 --> 00:06:54,750 like this video be sure to give it a 201 00:06:53,610 --> 00:06:55,830 thumbs up I appreciate it thumbs down 202 00:06:54,750 --> 00:06:56,819 for the opposite click to subscribe but 203 00:06:55,830 --> 00:06:58,020 if you have any stay tuned for more 204 00:06:56,819 --> 00:07:01,460 content like this this is science studio 205 00:06:58,020 --> 00:07:01,460 thanks for learning with us 206 00:07:03,290 --> 00:07:10,989 [Music] Quantum Computers Explained - What are Qubits Trusty white board here. In order to understand quantum computing, we've gotta run through binary computing. 1s and 0s. Only two possible outcomes. We have transistors in on and off states to control the flow of voltage; basically closing and opening circuits like valves control the flow of water through pipes. It's always easier to picture circuits in this way. If the circuit is open, then no pathway exists and current (or, in this case, water) does not flow. But if the circuit is closed, the pathway is completed and water flows unhindered. Transistors are these “valves” or “on/off” switches. For binary systems, like the computers and phones you're using to watch this video, binary transistors open and close to indicate 1 and 0. I explain it a bit more in this video right here. For now, just know that, if threshold voltage is not reached, a gap in the current is created indicating a “0 for FALSE.” Whether it's a 1 or 0 really depends on the algorithm being used. They'll always be opposites. For our examples in this video, 1 = True = closed circuit, and 0 = False = open circuit. This is how all data in modern computing systems is transmitted and processed. And you can imagine how billions of transistors opening and closing at billions of times per second can amount to some serious data computation. But quantum computers make PCs like this one behind me seem like basic calculators. They aren't binary systems per se, although we often use 1 and 0 to denote the range of values quantum bits, or “qubits” can denote. In a nutshell, “quantum,” in the term “quantum mechanics” defines the energy levels of small particles. And thanks to research done by Werner Heisenberg, Serge Haroche, and David Wineland, we now know that it also describes how an electron can be in two places at once. This is from where quantum computing is derived. Instead of 1s and 0s, regular bits, qubits can represent an infinite range of values between 1 and 0. And unlike the classical counterpart, qubits can be physical objects like electrons and photons. Imagine a compass with one pole denoted 1 and the other pole denoted 0. The needle of the compass can swing wherever it wants within the system – but it can never point to anything higher than one and lower than zero. Instead, it can point to areas in-between the two poles and represent the likelihood of either becoming a 1 or 0 once the qubit is processed. This area in-between is what's known as “superposition.” When we read and interpret classical three-bit binary data streams, we understand that eight outcomes are possible. Since there are two possible states and 3 bits, 2 raised to n (where n is 3) = 8. So eight possible outcomes here; all probabilities of which must equal 1. So there's a 100% chance that a three-bit binary system will yield one of these values (since they're the only values possible with three digits and two numbers). A quantum three-bit system works a bit different, however. Since each qubit can denote any complex number between 0 and 1, then the sum of the squares of each complex probability must equal 1 for a 100% probability. When we make a measurement of a 3-bit quantum system, the values of the particles in each orientation collapse to a classical state of binary. But the computational power of a three-bit quantum computer far-exceeds that of classical systems. Where binary systems require 2 raised to the power N bits, quantum computers can express the same amount of information in just N qubits. For scale, just a 30-bit computer is capable of nearly 10 teraflops of floating point performance. That's 10 trillion floating operations per second which, in the real world, would require billions of transistors. But like I said in this video right here, quantum computers aren't as practical for every-day users as you might think. Streaming, editing, and even gaming won't benefit much from quantum PCs in the current state; and they get extremely hot. They have to be cryogenically cooled. They must also be shielded from the outside world, since even the smallest magnetic disturbances can offset a qubit's reading and promote decoherence. They're extremely large, expensive, and difficult to maintain, and are more-or-less used for large probability and research operations today. The viability of these quantum computers will change as our technology and infrastructure does, but I expect we'll still be relying on the binary system for many years to come. They just work. We don't have to worry about quantum decoherence, overheating, and insane shielding. But much like early binary computers, quantum computers today are very large. Who knows? In fifty years, we may have shrunken an entire system to the size of this. If we had enough computational qubits in this as we do classical transistors, imagine the potential. |
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